The present invention relates to a semiconductor computing circuit for performing computations on analog values and a computing apparatus using the same, and more particularly to a semiconductor computing circuit for computing an absolute difference between two analog signal values and a computing apparatus for computing a Manhattan distance which is a measure of a similarity to a reference pattern.
With the advance of computer technology, dramatic strides have been made in data processing technology in recent years. However, if flexible information processing, such as visual recognition or voice recognition as is done by humans, is to be implemented using a computer, it is said that, with today""s digital computers, it is almost impossible to provide computation results in real time. One reason for this is that much of the information we handle in our daily lives is in the form of analog quantities and, when these quantities are represented by digital data, not only does the amount of data become prohibitively large but also the data is inaccurate and ambiguous. It can be said that the problem of today""s information processing systems lies in the fact that extremely redundant analog data are converted to digital quantities and rigorous digital computations are performed one by one. Furthermore, in today""s information processing systems, computing circuits for performing digital computations and memory for holding digital data are provided as separate elements, and as a result, a long computation time is required because of the bus bottleneck between the computing circuit and the memory.
To solve such problems, attempts are being made to achieve information processing more analogous to the human brain by taking in information from the external world in its original form, i.e., in form of analog quantities, and by performing computations directly on the analog quantities. One such approach to information processing involves evaluating the similarity between an input signal pattern and a prestored analog pattern. More specifically, a large number of voice or image code patterns are stored in advance and, by comparing the input signal pattern with each code pattern for similarity, a code pattern having the highest similarity is selected. Similarity is measured using the Euclidean distance or the Manhattan distance (the sum of absolute differences); since the computation of the Manhattan distance can be accomplished by calculating only differences whereas the computation of the Euclidean distance requires a multiplication as well, and since, in such processing, evaluating the degree of correlation is of major concern and mathematically rigorous computations are not required, it is common to measure similarity using the Manhattan distance. The semiconductor computing circuit of the present invention lends itself to computation of the Manhattan distance.
Various methods have been proposed for performing computations directly on analog quantities. For example, Japanese Unexamined Patent Publication No. 3-6679 discloses a neuron MOS transistor which behaves like a neuron, a nerve cell, and performs summation of a plurality of analog input signals. Japanese Unexamined Patent Publication No. 6-53431 discloses a computing circuit utilizing this neuron MOS transistor. Further, Republished Patent No. WO96/30853 discloses a semiconductor computing circuit which uses two MOS transistors having a floating gate, with their sources or drains connected together, and which, by applying two analog signals and their difference signal to control gates, computes an absolute-value voltage representing the difference between the two analog signals.
When computing the Manhattan distance, usually, the code pattern is predetermined and the similarity between the input signal and the predetermined code pattern is evaluated; once the code pattern is set in the computing circuit, it is desirable that the computation be performed continuously on various image input signals, and it is rare that the code pattern is changed. However, the computing circuit disclosed in the above cited Republished Patent No. WO96/30853 requires that two analog signals or their processed signals be input for each computation. To meet this requirement, a memory for holding code patterns must be provided, and signals read from the memory must be set in each computing cell of the computing circuit each time the computation is performed; this not only increases the computation time but also presents the problem that the wiring for delivering the signals read from the memory to the respective computing cells of the computing circuit becomes enormous. Moreover, if the code pattern is stored in digital signal form, a D/A converter for converting it into an analog signal must be provided, which causes the problem that the amount of circuitry increases.
It is an object of the present invention to provide a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed.
To achieve the above object, the semiconductor computing circuit of the present invention comprises two MOS transistors, each having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrodes are connected together, and a write circuit for writing a desired voltage to each MOS transistor.
More specifically, the semiconductor computing circuit of the present invention is characterized by the provision of: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a first write circuit for writing a desired voltage to the floating gate of the first MOS transistor; and a second write circuit for writing a desired voltage to the floating gate of the second MOS transistor.
When computing an absolute-value voltage representing the difference between a first signal voltage VM and a second signal voltage VX by using the semiconductor computing circuit, first the potential at one floating gate is set to V. and the potential at the other floating gate to VDDxe2x88x92VM while applying a prescribed voltage (for example, supply voltage VDD) to the two floating gates. In this condition, when VDDxe2x88x92VX is applied to the one control gate and VX to the other control gate, the absolute-value voltage representing the difference between the first signal voltage VM and the second signal voltage VX is output.
More specifically, the semiconductor computing circuit of the present invention for computing an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, an absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.
When the difference between the actually obtained voltage and the ideal voltage, occurring due to the ratio of MOS transistor gate capacitance to floating gate to control gate coupling capacitance, becomes a problem, each potential to be written by the write circuit in the above configuration is, for example, multiplied by a positive constant xcex3 smaller than 1 which is related to the coupling capacitance ratio. To obtain the value of the potential multiplied by the constant xcex3 for writing, the write circuit comprises a readout circuit for reading a voltage on a floating gate of a dummy MOS transistor which is equivalent to the first or second MOS transistor, and a correction voltage computing circuit for computing an output difference of the readout circuit occurring when two voltages, the difference between which is equal to the voltage to be written to the first or second MOS transistor, are applied one after the other to the control gate of the dummy MOS transistor, and the write circuit writes a voltage equal to the output difference to the first or second MOS transistor. This output difference corresponds to the value of the potential to be written, multiplied by the constant xcex3.
Alternatively, in the above configuration, the voltage to be applied to the control gates when setting the potentials of the respective floating gates by the write circuit, and the voltages to be applied to the respective control gates when performing computation, may be divided by the constant xcex3.
The first and second MOS transistors may be constructed using N-channel MOS transistors or P-channel MOS transistors; in the case of N-channel MOS transistors, the high-level supply voltage VDD is applied as the prescribed voltage, and in the case of P-channel MOS transistors, the low-level supply voltage VSS is applied as the prescribed voltage.
In the semiconductor computing circuit of the present invention, once the floating gate has been set at a potential related to the first signal voltage, the computation can be performed by just inputting the second signal voltage and a voltage related to it without having to use the first signal voltage or a voltage related to it. Accordingly, since the potential once set in the floating gate is maintained in its entirety, there is no need to apply the first signal voltage or a voltage related to it when performing the computation, unless the first signal voltage is changed.
The present invention also provides a computing apparatus for computing the sum of absolute differences between corresponding signals in a first signal group and a second signal group each consisting of a predetermined number of signals, comprising: an individual absolute-value computing circuit having semiconductor computing circuits corresponding in number to the predetermined number of signals and each identical with the semiconductor computing circuit of the present invention; and a summing circuit for computing the sum of outputs of the semiconductor computing circuits in the individual absolute-value computing circuit.
As described above, in each semiconductor computing circuit used in the computing apparatus of the present invention, once the floating gate of the semiconductor computing circuit has been set at a potential related to the first signal voltage, there is no need to apply the first signal voltage or a voltage related to it when performing the computation; this eliminates the need to provide a separate memory for storing the signals of the first signal group corresponding to code patterns, and also the signal path from the memory to the gate of each semiconductor computing circuit can be eliminated.
The summing circuit comprises, for example, a plurality of capacitors each having two terminals, the first terminal and the second terminal, wherein the second terminals of the capacitors are connected together to form a common second terminal; and a MOS transistor whose gate electrode is formed from an extended portion of the common second terminal, wherein the source electrodes of the semiconductor computing circuits in the individual absolute-value computing circuit are respectively connected to the first terminals.
As described above, once the floating gate of the semiconductor computing circuit has been set at a potential related to the first signal voltage, there is no need to apply the first signal voltage or a voltage related to it when performing the computation. Accordingly, the write circuit may be made removable so that the write circuit can be removed from the computing apparatus after writing the desired potential to the floating gate using the write circuit.